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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADP1148, ADP1148-3.3, ADP1148-5 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1997 high efficiency synchronous step-down switching regulators functional block diagram q r s v th1 v in sense(C) v th2 1.25v off-time control 100k v 13k v b v in p-drive sense(+) sense(C) g 4 6 c t i th shutdown 8 1 3 ADP1148 10mv to 150mv c v fb int v cc reference 5 10 t n-drive pwr gnd 14 12 adjustable version v fb 9 7 s 1 q r s 2 v sleep signal gnd 11 non-overlap drive features operation from 3.5 v to 18 v input voltage ultrahigh efficiency > 95% low shutdown current current mode operation for excellent line and load transient response high efficiency maintained over wide current range logic controlled micropower shutdown short circuit protection very low dropout operation synchronous fet switching for high efficiency adaptive nonoverlap gate drives applications notebook and palmtop computers portable instruments battery operated digital devices industrial power distribution avionics systems telecom power supplies gps systems cellular telephones general description the ADP1148 is part of a family of synchronous step-down switching regulator controllers featuring automatic sleep mode to maintain high efficiencies at low output currents. these devices drive external complementary power mosfets at switching frequencies up to 250 khz using a constant off-time current-mode architecture. v in int v cc i th c t s-gnd p-drive sense(+) sense(C) shutdown n-drive p-gnd ADP1148 + + p-ch irf7204 n-ch irf7403 1000pf c t 470pf r c 1k v c c 3300pf c1 10bq040 l* 62 m h r sense ** 0.05 v +c out 390 m f c in 100 m f v in (5.2v to 18v) 1 m f 10nf 0v = normal >1.5v = shutdown *coiltronics ctx-68-4 **krl sl-1-c1-0r050l v out 5v/2a figure 1. high efficiency step-down converter figure 2. ADP1148-5 typical efficiency the constant off-time architecture maintains constant ripple current in the inductor, easing the design of wide input range converters. current-mode operation provides excellent line and load transient response. the operating current level is user programmable via an external current sense resistor. the ADP1148 incorporates automatic power saving sleep mode operation when load currents drop below the level re- quired for continuous operation. in sleep mode, standby power is reduced to only about 2 mw at v in = 10 v. in shutdown, both mosfets are turned off. typical applications load current ?a 100 85 70 0.02 2 95 90 80 75 efficiency ?% 0.2 v in = 6v v in = 10v figure 1 circuit
C2C rev. a ADP1148, ADP1148-3.3, ADP1148-5Cspecifications electrical characteristics parameter symbol conditions 2 min typ max units feedback voltage ADP1148 only v 10 v in = 9 v 1.21 1.25 1.29 v feedback current ADP1148 only i 10 0.2 1.0 m a regulated output voltage v out v in = 9 v ADP1148-3.3 i load = 700 ma 3.23 3.33 3.43 v ADP1148-5 i load = 700 ma 4.9 5.05 5.2 v output voltage line t a = +25 c, v in = 7 v to 12 v, regulation dv out i load = 50 ma C40 +40 mv output voltage load regulation dv out ADP1148-3.3 5 ma < i load < 2 a 40 65 mv ADP1148-5 5 ma < i load < 2 a 60 100 mv sleep mode output ripple dv out i load = 0 a 50 mv p-p input dc supply current 3 i q t a = +25 c normal mode v in = 4 v < v in < 18 v 1.6 2.3 ma sleep mode (ADP1148-3.3) v in = 4 v < v in < 18 v 160 250 m a sleep mode (ADP1148-5) v in = 4 v < v in < 18 v 160 250 m a shutdown v shutdown = 2.1 v, 10 20 m a 4 v < v in < 15 v current sense threshold v 8 Cv 7 v 9 = v out /4 + 25 mv (forced), voltage 4 v 7 = 5 v, t a = +25 c25mv ADP1148 only v 9 = v out /4 mv C 25 mv (forced), v 7 = 5 v 130 150 170 mv ADP1148-3.3 v 7 = v out + 100 mv (forced) 25 mv v 7 = v out C 100 mv (forced) 130 150 170 mv ADP1148-5 v 7 = v out + 100 mv (forced 25 mv v 7 = v out C 100 mv (forced) 130 150 170 mv shutdown pin threshold ADP1148-3.3, ADP1148-5 v 10 t a = +25 c 0.6 0.8 2.0 v shutdown pin input current i 10 0 v < v shutdown < 8 v, v in = 18 v 1.2 5 m a c t pin discharge current i 4 t a = +25 c, v out in regulation, v 7 = v out , 506590 m a v out = 0 v 2 10 m a off-time t off c t = 390 pf, i load = 700 ma 4 5 6 m s driver output transition t r , t f c l = 3000 pf (pins 1, 14) times v in = 6 v, t a = +25 c 100 200 ns notes 1 all limits at temperature extremes are guaranteed via correlation using standard quality control methods. specifications subjec t to change without notice. 2 t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ADP1148ar, ADP1148ar-3.3, ADP1148ar-5: t j = t a + (p d 110 c/w) ADP1148an, ADP1148an-3.3, ADP1148an-5: t j = t a + (p d 70 c/w) 3 dynamic supply current is higher due to the gate charge being delivered at the switching frequency. the allowable operating fre quency may be limited by power dissipation at high input voltages. 4 the ADP1148 version is tested with external feedback resistors, setting the nominal output voltage to 3.3 v. specifications subject to change without notice. (0 8 c t a +70 8 c, 1 v in = 10 v, v shutdown = 0 v, unless otherwise noted. see figure 17.)
C3C rev. a ADP1148, ADP1148-3.3, ADP1148-5 electrical characteristics parameter symbol conditions 2 min typ max units feedback voltage ADP1148 only v 10 v in = 9 v 1.20 1.25 1.30 v regulated output voltage v out v in = 9 v ADP1148-3.3 i load = 700 ma 3.17 3.33 3.4 v ADP1148-5 i load = 700 ma 4.85 5.05 5.2 v input dc supply current 3 i q normal mode v in = 4 v < v in < 18 v 1.6 2.6 ma sleep mode (ADP1148-3) v in = 4 v < v in < 18 v 160 280 m a sleep mode (ADP1148-5) v in = 6 v < v in < 18 v 160 280 m a shutdown v shutdown = 2.1 v, 10 24 m a 4 v < v in < 12 v current sense threshold voltage 4 v 8 Cv 7 ADP1148 only v 9 = v out /4 + 25 mv (forced), 0 mv v 7 = 5 v v 9 = v out /4 C 25 mv (forced), 115 150 175 mv v 7 = 5 v ADP1148-3.3 v 7 = v out + 100 mv (forced) 0 mv v 7 = v out C 100 mv (forced) 115 150 175 mv ADP1148-5.0 v 7 = v out + 100 mv (forced) 0 mv v 7 = v out C 100 mv (forced) 115 150 175 mv shutdown pin threshold v 10 ADP1148-3.3, ADP1148-5 0.55 0.8 2 v off-time t off c t = 390 pf, i load = 700 ma 4 5 6.2 m s notes 1 all limits at temperature extremes are guaranteed via correlation using standard quality control method. 2 t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ADP1148ar, ADP1148ar-3, ADP1148ar-5: t j = t a + (p d 110 c/w) ADP1148an, ADP1148an-3, ADP1148an-5: t j = t a + (p d 70 c/w) 3 dynamic supply current is higher due to the gate charge being delivered at the switching frequency. the allowable operating fre quency may be limited by power dissipation at high input voltages. 4 the ADP1148 version is tested with external feedback resistors setting the nominal output voltage to 3.3 v. specifications subject to change without notice. absolute maximum ratings input supply voltage (pin 3) . . . . . . . . . . . . . C0.3 v to +20 v continuous output currents (pins 1, 14) . . . . . . . . . . 50 ma sense voltages (pins 7, 8) . . . . . . . . . . . . . . . . C0.3 v to v cc operating temperature range . . . . . . . . . . . . 0 c to +70 c extended commercial temperature range . . C40 c to +85 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . 300 c (C40 8 c t a +85 8 c, 1 v in = 10 v, v shutdown = 0 v, unless otherwise noted. see figure 17.) ordering guide output package package model voltage description option ADP1148an adj plastic dip n-14 ADP1148ar adj small outline package so-14 ADP1148an-3.3 3.3 v plastic dip n-14 ADP1148ar-3.3 3.3 v small outline package so-14 ADP1148an-5 5 v plastic dip n-14 ADP1148ar-5 5 v small outline package so-14
ADP1148, ADP1148-3.3, ADP1148-5 C4C rev. a caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADP1148, ADP1148-3.3, ADP1148-5 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin function descriptions pin # mnemonic function 1 p-channel drive high current gate drive for top p-channel mosfet. the voltage swing at pin 4 is from v in to ground. 2 nc no connection. 3v in input voltage. 4c t external capacitor c t from pin 4 to ground sets the operating frequency. the frequency is also dependent on the ratio v out /v in . 5 int v cc internal supply voltage, nominally 3.3 v. must be decoupled to signal ground. do not externally load this pin. 6i th error amplifier decoupling point. the current comparator threshold increases with the pin 7 voltage. 7 senseC connects to internal resistive divider that sets the output voltage in ADP1148-3.3 and ADP1148-5 versions. pin 7 is also the (C) input for the current comparator. 8 sense+ the (+) input for the current comparator. a built-in offset between pins 7 and 8, in conjunction with r sense , sets the current trip threshold. 9v fb for the ADP1148 adjustable version, pin 9 serves as the feedback pin from an external resistive divider used to set the output voltage. on ADP1148-3.3 and ADP1148-5 versions, this pin is not used. 10 shutdown taking pin 10 of the ADP1148, ADP1148-3.3 or ADP1148-5 high holds both mosfets off. must be at ground potential for normal operation. 11 signal gnd small signal ground. must be routed separately from other grounds to the (C) terminal of c out . 12 power gnd driver power ground. connects to source of n-channel mosfet and the (C) terminal of c in . 13 nc no connection. 14 n-channel drive high current drive for bottom n-channel mosfet. the voltage swing at pin 13 is from ground to v in . pin configurations 14-lead plastic dip 14-lead plastic so 14 13 12 11 10 9 8 1 2 3 4 7 6 5 top view (not to scale) nc = no connect p-drive signal gnd power gnd nc n-drive nc v in c t ADP1148 sense(+) v fb * shutdown int v cc i th sense(? *fixed output versions = sd1 warning! esd sensitive device
typical performance characteristicsCADP1148, ADP1148-3.3, ADP1148-5 C5C rev. a maximum output current C a 200 0 0 5 123 4 150 100 50 r sense C m v figure 3. selecting r sense vs. maxi- mum output current output current ?a efficiency/loss ?% 100 95 80 0.01 0.03 3.0 0.1 0.3 1.0 90 85 i q gate charge i 2 r figure 6. typical efficiency losses load current C a d v out C mv 60 40 C60 0 0.5 2.5 1.0 1.5 2.0 20 0 C20 C40 figure 1 circuit v in = 6v v in = 12v figure 9. load regulation l = 50 m h r sense = 0.02 v l = 25 m h r sense = 0.02 v l = 50 m h r sense = 0.05 v (v in Cv out ) voltage C v 1000 800 0 05 234 1 600 400 200 c out C m f figure 5. selecting minimum output capacitor vs. (v in Cv out ) and inductor d v out C mv v in +40 +20 C60 04 16 6 8 10 12 14 0 C20 C40 figure 1 circuit i load = 1a i load = 0.1a figure 8. ADP1148-5 output voltage change vs. input voltage v shutdown = 2v input voltage C v supply current C m a 30 0 46 20 81012141618 25 20 15 10 5 figure 11. supply current in shutdown frequency ?khz 1000 0 0 300 100 200 400 200 800 600 v in = 12v v in = 10v v in = 7v v sense = v out = 5v capacitance ?pf figure 4. operating frequency vs. timing capacitor value input voltage C v 100 86 80 020 4 8 12 16 98 88 84 82 92 90 96 94 efficiency C % figure 1 circuit i load = 1a i load = 100ma figure 7. efficiency vs. input voltage input voltage ?v supply current ?ma 1.6 0.0 46 20 active mode sleep mode 8 1012141618 1.4 0.8 0.6 0.4 0.2 1.2 1.0 figure 10. dc supply current
(v in Cv out ) C v 12 normalized frequency 12 46810 1.8 1.6 0.0 0.8 0.6 0.4 0.2 1.4 1.0 1.2 0 8 c 25 8 c 70 8 c figure 12. operating frequency vs. (v in Cv out ) temperature C 8 c 155 120 0 100 25 70 85 150 145 140 135 sense voltage C mv 130 125 maximum threshold figure 15. current sense threshold voltage operating frequency ?khz gate charge current ?ma 30 0 20 50 260 80 110 140 170 200 230 25 20 15 10 5 qn+qp = 50nc qn+qp = 100nc figure 13. gate charge supply current output voltage C v off time C m sec 80 30 0 0.3 0.5 5.0 1.0 1.5 2.0 2.5 3.0 3.3 3.5 4.0 4.5 70 40 20 10 60 50 5v 3.3v figure 14. off time vs. v out ADP1148, ADP1148-3.3, ADP1148-5Ctypical performance characteristics C6C rev. a
ADP1148, ADP1148-3.3, ADP1148-5 C7C rev. a applications the ADP1148 uses a current-mode, constant off-time structure to switch a pair of external complementary n- and p-channel mosfets. the operating frequency of the device is deter- mined by the value of the external capacitor connected to the c t pin. the output voltage is sensed by an internal voltage divider which is connected to the sense(C) pin (ADP1148-3.3 and ad1148-5) or an external voltage divider returned to v fb (ADP1148). a voltage comparator v, and a gain block g compare the values of the divided output voltage with a reference voltage of 1.25 v. to maximize the efficiency, the ADP1148 automatically switches between two operational modes, power-saving and continuous. the flip-flop 1 is the main control element when the device is in its power-saving mode while the gain block is the main con- trol when the output voltage moves to continuous mode. during the continuous mode of the pmos switch on-cycle, the current comparator c, monitors the voltage between sense(C) and sense(+). when the voltage level reaches the threshold level, the p drive output is switched to v in which turns off the p-channel mosfet. the timing capacitor c t is now able to discharge at a rate determined by the off-time controller. the discharge current is made to be proportional to the value of the output voltage (measured at the sense(C) pin) to model the inductor current which decays at a rate which is proportional to the out- put voltage. while the timing capacitor is discharging, the n drive output goes to v in , turning on the n-channel mosfet. when the voltage level on the timing capacitor has discharged to the threshold voltage level v th1 , comparator t switches setting flip-flop 1. this forces the n drive to go off and the p drive output low and subsequently turns the p-channel mosfet on. the sequence is then repeated. as load current increases, the output voltage starts to reduce. this results in the output of the gain circuit increasing the level of the current comparator thresh- old, thus tracking the load current. at very low load currents the power-saving sequence will be interrupted by the set of flip-flop 2, by voltage comparator b, which also monitors the voltage across r sense . when the load current decreases to half the designed inductor ripple current, the voltage across r sense will reverse polarity. when this hap- pens, comparator b will set the q-bar output of flip-flop 2, which will go to logic zero state and interrupt the cycle-by-cycle operation and inhibit the output fet-driver. the output of the power supply storage capacitor will slowly be drained by the load and the output voltage starts decreasing. when this decreased voltage exceeds the v os of comparator v, this in turn will reset flip-flop 2, and normal cycle-by-cycle operation will resume. if the load is very small, it will take a long time for flip- flop 2 to reset, and during that time the oscillator capacitor may discharge below v th2 . at the point at which the timing capacitor discharges below v th2 , comparator s trips causing the internal sleep-bar to go low. the circuit is now in sleep mode and the n-channel power mosfet remains turned off. while the circuit remains in this mode, a significant amount of the circuit of the ic is turned off dropping the ground current from approximately 1.6 ma to a level of 160 m a. in this state the load current is supplied by the output capacitor. the sleep mode is also terminated by the reset of flip-flop 2. to prevent both the external mosfets from ever being turned on simultaneously, feedback is incorporated to sense the state of the driver output pins. before the n drive output can go high, the p drive output must also be high. likewise, the p drive output is unable to go low while the n drive output is high. by utilizing a constant off-time structure, the device operation is a function of the input voltage. to limit the effect of frequency variation as the device approaches dropout, the controller begins to increase the discharge current as v in drops below v out +1.5 v. while the device is in drop- out, the p-channel mosfet is on constantly. r sense selection for output current the choice of r sense is based on the required output current. the ADP1148 current comparator has a threshold range which extends from 0 mv to a maximum of 150 mv/r sense . the current comparator threshold sets the peak of the inductor cur- rent, yielding a maximum output current i max equal to the peak value less half the peak-to-peak ripple current. the ADP1148 operates effectively with values of r sense from 20 m w to 200 m w . a graph for selecting r sense versus maximum output current is given in figure 3. solving for r sense and allowing a margin for variations in the ADP1148 and external component values yields: r sense = 100 mv / i max the peak short circuit current, (i sc(pk) ) tracks i max . once r sense has been chosen, i sc(pk) can be predicted from the fol- lowing equation: i sc(pk) = 150 mv / r sense the load current, below which power-saving mode commences (i power-saving ) is determined by the offset in comparator b and the value of the inductor chosen. comparator b is designed to have approximately 5 mv offset. this offset and the inductor can now be used to predict the power saving mode current as follows: i power-saving ~ 5 mv / r sense + v o t off /2 l the ADP1148 automatically extends t off during a short circuit to provide adequate time for the inductor current to decay be- tween switch cycles. the resulting ripple current causes the average short circuit current, i sc(avg) , to be lowered to approxi- mately i max . l and c t selection for operating frequency the ADP1148 uses a constant off-time architecture with t off determined by an external timing capacitor c t . each time the p-channel mosfet switch turns on, the voltage on c t is reset to approximately 3.3 v. during the off time, c t is discharged by a current which is proportional to v out . the voltage on c t is analogous to the current in inductor l, which likewise decays at a rate proportional to v out . therefore, the inductor value must track the timing capacitor value. the value of c t is calculated from the preferred continuous mode operating frequency: c t = 1/2.6 10 4 f assumes v in = 2 v out (figure 1 circuit). a graph for selecting c t versus frequency including the effects of input voltage is given in figure 5. *component, voltage, current, etc., values are in si-units (international standard) unless otherwise indicated.
ADP1148, ADP1148-3.3, ADP1148-5 C8C rev. a as the operating frequency is increased, the gate charge losses will cause reduced efficiency (see efficiency section). the full formula for operating frequency is given by: f = ( 1 C v out /v in )/ t off where t off = 1.3 10 4 c t v reg /v out. v reg is the desired output voltage (i.e., 5 v or 3.3 v), v out is the measured output voltage. thus, v reg /v out = 1 in regulation. note that as v in reduces, the frequency also decreases. when the input to output voltage differential drops below 1.5 v, the ADP1148 reduces t off by increasing the discharge current in c t . this prevents audible operation before the device goes into dropout. once the frequency has been set by c t , the inductor l must be chosen to provide no more than 25 mv/r sense of peak-to-peak inductor ripple current. this is set by the equation: 25 mv r sense = v out t off l min or l min = v out t off r sense 25 mv substituting for t off from above gives the minimum required inductor value of: l min = 5.1 10 5 r sense c t v reg as the inductor value increases above the minimum value, the esr requirements for the output capacitor are relaxed at the expense of efficiency. if too small an inductor is used, the induc- tor current will decrease past zero and change polarity. a result of this occurrence will be that the ADP1148 may not be in power saving mode operation and efficiency will be significantly reduced at low currents. inductor core once the minimum value for l is known, the selection of the inductor must be made. high efficiency converters - p generally cannot accommodate the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy (mpp), or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses de- crease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss, so design goals can focus on copper loss and preventing saturation. ferrite core material saturates hard, which causes the inductance to collapse abruptly when the peak design current is exceeded. this results in a sharp increase in inductor ripple current and subsequently output voltage ripple which can cause the power saving mode operation to be falsely triggered in the ADP1148. to prevent this action from occurring, do not allow the core to saturate! molypermalloy from magnetics, inc., is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manufacturer is kool m m . toroids are very space efficient, especially when you can use several layers of wire. because they generally lack a bobbin, mounting is more difficult. many new designs for surface mount components are also available from coiltronics which do not increase the component height significantly. power mosfet two external power mosfets must be selected for use with the ADP1148, a p-channel mosfet for the main switch, and an n-channel mosfet for the synchronous switch. the main selection parameters for the power mosfets are the threshold voltage v gs(th) and on resistance r ds(on) . the minimum input voltage dictates whether standard threshold or logic-level threshold mosfets must be used. for v in > 8 v, standard threshold mosfets (v gs(th ) < 4 v) may be used. if v in is expected to drop below 8 v, logic-level threshold mosfets (v gs(th) < 2.5 v) are strongly recommended. when logic-level mosfets are used, the ADP1148 supply voltage must be less than the absolute maximum v gs rating for the mosfets (e.g., > 8 v of irf7304. the maximum output current i max determines the r ds(on) requirement for the two power mosfets. when the ADP1148 is operating in continuous mode, the simplifying assumption can be made that one of the two mosfets is always conducting the average load current. the duty cycles for the mosfet and diode are given by: p-channel duty cycle = v out /v in n-channel duty cycle = ( v in C v out )/ v in from the duty cycle the required r ds(on) for each mosfet can be derived: p-ch rds(on) = ( v in p p )/[ v out i max 2 (1 + d p )] n-ch rds(on) = ( v in p n )/[( v in C v out ) i max 2 (1+ d n )] where p p and p n are the allowable power dissipations and d p and d n are the temperature dependency of r ds(on) . p p and p n will be determined by efficiency and/or thermal requirements (see efficiency). (1+d) is generally given for a mosfet in the form of a normalized r ds(on) vs. temperature curve, but d = 0.007/ c can be used as an approximation for low voltage mosfets. the schottky diode d1 shown in figure 1 conducts only during the deadtime between the conduction of the two power mosfets. d1s purpose is to prevent the body-diode of the n-channel mosfet from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. d1 should be selected for forward voltage of less than 0.5 v when conducting i max . c in and c out selection in continuous mode, the source current of the p-channel mosfet is a square wave of duty cycle v out /v ln . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms ca- pacitor current is given by: c in required i rms ~ [ v out ( v in C v out )] 0.5 i max /v in this formula has a maximum at v in = 2 v out , where i rms = i out /2. this simple worst case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advis- able to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. all trademarks are the property of their respective holders.
ADP1148, ADP1148-3.3, ADP1148-5 C9C rev. a an additional 0.1 m f C 1 m f ceramic bypass capacitor is advised on v in pin 3 parallel with c in . the selection of c out is driven by the required effective series resistance (esr). the esr of c out must be less than twice the value of r sense for proper operation of the ADP1148: c out required esr < 2 r sense. optimum efficiency is obtained by making the esr equal to r sense . as the esr is increased up to 2 r sense , the efficiency degrades by less than 1%. manufacturers such as sprague, and united chemmicon should be considered for high performance capacitors. the os-con semiconductor dielectric capacitor has the lowest esr for its size, at a somewhat higher price. once the esr requirement for c out has been met, the rms current rating generally far ex- ceeds the i ripple(p-p) requirement. in surface-mount applications multiple capacitors may have to be paralleled to meet the capacitance, esr, or rms current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are both available in surface-mount configurations. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. consult the manufacturer for other specific recommendations. the c o output filter capacitor has to be sized correctly to avoid excessive ripple voltages at low frequencies. see figure 5 for output capacitor selection. transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d1 load esr , where esr is the effective series resistance of c out. d1 load also begins to charge or discharge c out until the regulator loop adapts to the current change and returns v out to its steady- state value. during this recovery time v out can be monitored for overshoot or ringing which would indicate a stability prob- lem. the external components on the i th pin shown in the figure 1 circuit will prove adequate compensation for most applications. a second, more severe transient is caused by switching in loads with large (>1 mf) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , caus- ing a rapid drop in v out . no regulator can deliver enough cur- rent to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the inrush current to these capacitors below the current limit of the circuit. efficiency the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most im- provement. percent efficiency can be expressed as: % efficiency = 100% - ( l 1 + l 2 + l 3 +. . . ) where l 1, l 2, etc. are the individual losses as a percentage of input power. (for high efficiency circuits only small errors are incurred by expressing losses as a percentage of output power.) although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in ADP1148 circuits: 1) ADP1148 dc bias current, 2) mosfet gate charge currents, 3) i 2 r losses. 1) the dc supply current is the current which flows into v in pin 3 less the gate charge current. for v in = 10 v the ADP1148 dc supply current is 160 m a for no load, and increases pro- portionally with load up to a constant 1.6 ma after the ADP1148 has entered continuous mode. because the dc bias current is drawn from v in , the resulting loss increases with input voltage. for v in = 10 v the dc bias losses are generally less than 1% for load currents over 30 ma. however, at very low load currents the dc bias current accounts for nearly all of the loss. 2) mosfet gate charge currents result from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in which is typically much larger than the dc supply current. in continuous mode, i gatechg = f ( q p + q n ). the typical gate charge for a 100 m w n-channel power mosfet is 25 nc and for the p-channel about twice that value. this results in i gatechg = 7.5 ma in 100 khz continu- ous operation for a 2% to 3% typical midcurrent loss with v in = 10 v. note that the gate charge loss increases directly with both input voltage and operating frequency. this is the principal reason why the highest efficiency circuits operate at moderate frequencies. furthermore, it argues against using a larger mosfet than necessary to control i 2 r losses. 3) i 2 r losses are easily predicted from the dc resistances of the mosfet, inductor, and current shunt. in continuous mode the average output current flows through l and r sense , but is chopped between the p-channel and n- channel mosfets. if the two mosfets have about the same r ds(on) , the resistance of one mosfet can be simply summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 100 m w , r l = 150 m w , and r sense = 50 m w , then the total resistance is 300 m w . this results in losses ranging from 3% to 10% as the output current increases from 0.5 a to 2 a. i 2 r losses cause the efficiency to roll-off at high output currents. figure 6 shows how the efficiency losses in a typical ADP1148 regulator. the gate charge loss is responsible for the majority of the efficiency lost in the midcurrent region. if power saving mode operation was not employed at low currents, the gate charge loss alone would cause the efficiency to drop to unac- ceptable levels. with power saving mode operation, the dc supply current represents the lone (and unavoidable) loss component which continues to become a higher percentage as output cur- rent is reduced. as expected, the i 2 r losses dominate at high load currents. other losses including c in and c out esr dissi- pative losses, mosfet switching losses, schottky conduction losses during deadtime and inductor core losses, generally account for less than 2% total additional loss.
ADP1148, ADP1148-3.3, ADP1148-5 C10C rev. a design example as a design example, assume v in = 12 v (nominal), v out = 5 v, i max = 2 a, and f = 200 khz, r sense . c t , and l can immedi- ately be calculated: r sense = 100 mv /2 = 50 m w t off = (1/200 khz ) [1 C (5/12)] = 2.92 m s c t = 2.92 m s /(1.3 10 4 ) = 220 pf l min = 5.1 10 5 50 e -3 w 220 pf 5 v = 28 m h assume that the mosfet dissipations are to be limited to p n = 2p p = 250 mw. if t a = 50 c and the thermal resistance of each mosfet is 50 c/w, then the junction temperatures will be 63 c and d p = d p = 0.007 (63C25) = 0.27. the required r ds(on) for each mosfet can now be calculated: p-ch r ds(on) = 12 0.25/5 2 1.27 = 120 m w n-ch r ds(on) = 12 0.25/7 2 1.27 = 85 m w the p-channel requirement can be met by a irf7204. the n-channel requirement can be met by a irf7404. note that the most stringent requirement for the n-channel mosfet is with v out = 0 (i.e., short circuit). during a continuous short circuit, the worst case n-channel mosfet dissipation rises to: p n ~ i sc(avg) 2 r ds(on) (1 + d n ) with the 50 m w sense resistor i sc(avg) = 2 a will result, increas- ing the n-channel dissipation to 0.45 w at die temperature of 73 c. c in will require an rms current rating of at least 1 a at tempera- ture, and c out will require an esr of 50 m w for optimum efficiency. now allow v in to drop to its minimum value. at lower input voltages, the operating frequency will decrease and the p- channel will be conducting most of the time causing the power dissipation to increase. at v in(min) = 7 v, the frequency shifts to: f min = (1 C v out /v in )/ t off = (1/2.92 m s ) (1 C 5/7) = 98 khz and the p-channel power dissipation increases to: p p = (120 m w ) (2 a ) 2 (1.27) 5 v /7 v = 435 mw this last step is needed to ensure the maximum temperature of the p-channel mosfet is not exceeded. ADP1148 adjustable applications when an output voltage other than 3.3 v or 5 v is required, the ADP1148 adjustable version is used with an external resistive divider from v out to v fb pin 9. the regulated voltage is deter- mined by: v out = 1.25 (1 + r 2/ r 1) to prevent a stray pickup, a 100 pf capacitor is suggested across r1 located close to the ADP1148. auxiliary windings the ADP1148 synchronous switch removes the normal limita- tion that power must be drawn from the inductor primary wind- ing in order to extract power from auxiliary windings. with synchronous switching, auxiliary outputs may be loaded without regard to the primary output load, providing that the loop re- mains in continuous mode operation. output crowbar an added feature to using an n-channel mosfet as the syn- chronous switch is the ability to crowbar the output with the same mosfet. pulling the timing cap c t pin above 1.5 v when the output voltage is greater than the desired regulated value will turn on the n-channel mosfet and turn off the p-channel mosfet. a fault condition such as an external short between v in and v out , or an internal short of the p-channel device which causes the output voltage to go above a maximum allowable value can be detected by external circuity. turning on the n-channel mosfet when this fault is detected will cause large currents to flow and blow the system fuse. the n-channel mosfet needs to be sized so it will safely handle this over current condition. the typical delay from pull- ing the c t pin high and the n drive, pin 14 going high is 250 ns. note: under shutdown conditions, the n-channel mosfet is held off and pulling the c t pin high will not cause the n-channel mosfet to crowbar the output. a simple n-channel fet can be used as an interface between the overvoltage detect circuitry and the ADP1148 as shown in figure 16. ADP1148 int v cc c t 5 4 vn2222ll *from crowbar detect circuit *active when v gate = vin off when v gate = ground figure 16. output crowbar interface troubleshooting since efficiency is critical to ADP1148 applications, it is very important to verify that the circuit is functioning correctly in both continuous and power saving mode operation. the wave- form to monitor is the voltage on the timing capacitor c t pin. in continuous mode (i load > i power saving mode ), the voltage on the c t pin should be a sawtooth with a 0.9 v p-p swing. this voltage should never dip below 2 v as shown in figure 17a. when load currents are low (i load < i power saving mode ) , power saving mode operation occurs. the voltage on the c t pin now falls to ground for periods of time as shown in figure 17b. if the c t pin is observed falling to ground at high output currents, it indicates poor decoupling or improper grounding. refer to the board layout list. 3.3v 0v 3.3v 0v (a) continous mode operation (b) power-saving mode figure 17. c t waveforms
ADP1148, ADP1148-3.3, ADP1148-5 C11C rev. a board layout when laying out the printed circuit board, the following check list should be used to ensure proper operation of the ADP1148. these items are also illustrated graphically in the layout diagram of figure 18. check the following in your layout: 1) are the signal and power grounds segregated? the ADP1148 signal gnd (pin 11) must return to the (C) plate of c out . the power ground returns to the source of the n-channel mosfet, anode of the schottky diode, and (C) plate of c in , which should have as short lead len gths as possible. 2) does the ADP1148 sense(C), (pin 7), connect to a point close to r sense and the (+) plate of c out ? in adjustable versions the resistive divider r1, r2 must be connected be- tween the (+) plate of c out and signal ground. 3) are the sense(C) and sense(+) leads routed together with minimum pc trace spacing? the 1000 pf capacitor between pins 7 and 8 should be as close as possible to the ADP1148. 4) does the (+) plate of c in connect to the source of the p-channel mosfet as closely as possible? this capacitor provides the ac current to the p-channel mosfet. 5) is the input decoupling capacitor (1 m f) connected closely between v in (pin 3) and power gnd (pin 12)? this capacitor carries the mosfet driver peak currents. 6) is intv cc (pin 5) decoupled with a 10 nf capacitor to signal ground? 7) is the shutdown (pin 10) actively pulled to ground during normal operation? the shutdown pin is high imped- ance and must not be allowed to float. to prevent noise spikes from erroneously tripping the current comparator, a 1000 pf capacitor is needed across sense(C) and sense(+). p-drive nc v in c t int v cc i th sense(C) n-drive nc power gnd signal gnd shutdown v fb sense(+) ADP1148 3300pf 1k v d1 c in l r1 r2 c out 10nf c t 1 m f 1 2 3 4 5 6 7 14 13 12 11 10 9 8 n-channel 1000pf r1, r2 output divider required for adjustable version only. r sense C C v in v out p-channel nc = no connect figure 18. ADP1148 layout diagram (see board layout)
ADP1148, ADP1148-3.3, ADP1148-5 C12C rev. a p-drive nc v in c t int v cc i th sense(C) n-drive nc power gnd signal gnd shutdown v fb sense(+) ADP1148-3.3 c c 3300pf r c 1k v irf7403 d1 10bq040 v in 4v to 18v irf7204 c in 100 m f 20v *l 50 m h c out 220 m f 10v 3 2 avx 1000pf **r sense 0.1 v 10nf c t 300pf 1 m f 1 2 3 4 5 6 7 14 13 12 11 10 9 8 *coiltronics ctx50-2-mp **krl sp-1/2-a1-0r100j v out 3.3v/1a nc = no connect figure 19. ADP1148 low dropout, 3.3 v/1 a high efficiency regulator p-drive nc v in c t int v cc i th sense(C) n-drive nc power gnd signal gnd shutdown v fb sense(+) ADP1148 c c 6800pf r c 1k v irf7403 d1 10bq015 v in 4v to 9v irf7204 c in 220 m f 20v v out C5v/1.4a 25k v 1% 75k v 1% c out 220 m f 3 2 10v 200pf 1000pf **r sense 0.05 v 10nf c t 560pf 1 m f 1 2 3 4 5 6 7 14 13 12 11 10 9 8 *coiltronics ctx50-2-mp **krl sl-1-c1-0r05j *l 50 m h nc = no connect figure 20. 4 v to 9 v input voltage to C5 v/1.4 a regulator
ADP1148, ADP1148-3.3, ADP1148-5 C13C rev. a p-drive nc v in c t int v cc i th sense(C) n-drive nc power gnd signal gnd shutdown v fb sense(+) ADP1148 c c 3300pf r c 1k v irf7403 d1 10bq040 v in 5.2v to 14v irf7204 c in 100 m f 20v *l 50 m h r1b 43k v 1% r2 56k v 1% c out 220 m f 10v 3 2 os-con 100pf 1000pf **r sense 0.05 v 10nf c t 390pf 1 m f 1 2 3 4 5 6 7 14 13 12 11 10 9 8 r1a 33k v 1% 0v: v out = 3.3v 5v: v out = 5v vn2222ll v out 3.3v/2a or 5v/2a *coiltronics ctx50-2-mp **krl sl-1-c1-0r050j nc = no connect figure 21. logic selectable 5 v/1 a or 3.3 v/2 a high efficiency regulator
ADP1148, ADP1148-3.3, ADP1148-5 C14C rev. a outline dimensions dimensions shown in inches and (mm). 14-lead plastic dip (n-14) 14 17 8 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) pin 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 14-lead plastic so (so-14) 14 8 7 1 0.3444 (8.75) 0.3367 (8.55) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45
C15C
C16C c2219aC2C12/97 printed in u.s.a.

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